Optimum nested Miller compensation for low-voltage low-power CMOS amplifier design

Ka Nang Leung Ka Nang Leung,P.K.T Mok,Wing Hung Ki Wing Hung Ki

doi:10.1109/iscas.1999.780838

Optimum nested Miller compensation for low-voltage low-power CMOS amplifier design

Ka Nang Leung Ka Nang Leung, P.K.T Mok + Show 1 more

https://doi.org/10.1109/iscas.1999.780838

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Publication Date: May 30, 1999

Citations: 8

Affiliation: Hong Kong University of Science and Technology, University of Hong Kong

#Nested Miller Compensation #Null Resistor + Show 8 more

Abstract
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Abstract

An optimum structure of nested Miller compensation (NMC) is developed. The developed structure using a feedforward transconductance stage and null resistor on NMC, called NMCFNR, solves the bandwidth reduction and poor transient response problems of low-voltage low-power NMC amplifiers. For comparison, amplifiers compensated by NMC and NMCFNR have been fabricated. Experimental results show that NMCFNR improves the gain-bandwidth product, slew rate and settling time by more than three times with 8/spl deg/ increase on the phase margin and no increase of the power consumption. Moreover, it improves the negative power supply rejection ratio by at least 54 dB. The die area of the NMCFNR amplifier is about half of that of the NMC amplifier.

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