Optimum Design of Integrated Switched Capacitor Circuits Using 0.5-μM CMOS Technology

Abstract

Analytical optimization is used to create an optimized design of integrated switched-capacitor charge pump (CP) circuits. In integrated circuits design, voltage gain, output resistance, output ripple voltage, conversion efficiency, and capacitor sizing based on area constraints and power consumption are required for manufacturing. In this paper, an analytical optimization is performed and applied to conventional and bootstrapped techniques for fifth stages switched-capacitor charge pump circuits in order to optimize the parameter values. These circuits result in the appropriate function formulations that result in low power, minimum charge, and minimal area of the silicon chip. This paper describes an optimization method based on the improvement of these parameters that requires a trade-off between the above variables of the bootstrapped technique. The simulated circuits are designed in 0.5-μm complementary metal oxide semiconductor (CMOS) technology with 2 V devices. All of the integrated switched-capacitor circuits were designed with the same specification, which include 10 pF stage capacitance, 2 V supply voltage, clock frequency of 50 MHz and identical sizes of charge transfer switches (transistors). The bootstrapped technique that was implemented for all of the CPs' circuits has good efficiency of about (68.5 %), compared with (53 %) for conventional CPs' circuits.