Optimum design of high–density circuit boards

Abstract

AbstractThe method is discussed of determining wire width that minimizes the delay time and crosstalk of the average wiring length of wiring board under the condition that the wiring dimension is scaled down keeping the characteristic impedance of the transmission line constant. By employing the sending‐gate matching method suitable for the fine‐pattern wiring with high resistance, the equation for the relation between the wiring width and the average wiring length is determined from the condition of the gate count, terminal expansion, power consumption and LSI mount area for the multiple wiring layer board that places and routes many LSI chips. The delay time and crosstalk under high wiring resistance are analyzed with the distributed constant circuit model. Then the existence of the optimum wiring width that minimizes simultaneously the delay time and crosstalk for the average wiring length is proved.If the wiring width exceeds this value, the wiring length increases and the delay time and crosstalk are almost proportional to the wiring length. This is because the gate count determines the wiring count and the increase in wiring width increases the wiring board area. If the wiring width is less than the optimum value, only the wiring resistance increases. The wiring length does not decrease because the power consumption and LSI mount area determine the wiring board area. Moreover, the approximated equation that gives the optimum wiring width, delay time and crosstalk is determined to obtain the guidance for the design of the high‐density wiring board.