Abstract
The paper proposes several techniques for optimizing the JPEG2000 binary arithmetic encoder on very long instruction word (VLIW) architectures. Binary arithmetic coding (BAC) contains a large amount of conditional and sequential processing steps that make parallelism on VLIW devices difficult to realize. The paper illustrates an optimized software implementation that can software pipeline on a VLIW device. The Texas Instruments (TI) TMS320C64x digital signal processor (DSP) was chosen as the implementation platform. Results of our optimized code show a 2.4/spl times/ performance speed-up over a straightforward implementation of the arithmetic encoder as defined in the JPEG2000 standard.
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