Optimizing the IC delamination quality via six-sigma approach

Abstract

Integrated circuit (IC) delamination defects occur due to a poor adhesion between wafer passivation and the assembly-molding compound. Most of the components with minor delamination are not detected during the testing process, but they have the potential to cause functional failure in the application field. Unfortunately, reworking these components is not permitted, and the IC manufacturer can incur heavy costs if the suspected defective products have to be recalled. The industry is constantly striving to improve the delamination quality. However, this task is complicated and difficult. This is mainly because of insufficient knowledge of how to effectively detect when a delamination problem occurs. The quality control plan and reliability testing methods used in current processes are simply inadequate. This paper applies the six-sigma approach to assess the entire process, reduce the occurrence of delamination, and establishes a better quality control plan for the IC assembly process. This study also identifies the contact angle in order to quantify wafer surface contamination that results in delamination. The proposed method has been implemented in a semiconductor assembly factory in Taiwan. The analytical results of this study have demonstrated the feasibility of the proposed six-sigma approach and can be used as a disciplined problem solving approach for engineers for optimizing the IC process in the future.