Optimizing the hot carrier reliability of N-LDMOS transistor arrays

Abstract

Smart power management applications often require operation in the 20–30 V range. These applications combine a high performance BiCMOS process with a power lateral DMOS (LDMOS) driver. To obtain high drive current density and minimal on-resistance ( R dson), LDMOS devices are implemented in transistor arrays. Because of the high voltages and currents applied to these devices hot carrier degradation is a real reliability concern. This paper discusses several aspects of N-LDMOS hot carrier reliability including measurement techniques, degradation mechanism, and the effect of both one-dimensional (1-D) and two-dimensional (2-D) layout effects on the hot carrier degradation behavior of these devices. This paper focuses on device layout optimization rather than process changes since layout optimization has the advantage of improving performance without impacting other supported devices.