Abstract
Standard Taguchi methods such as orthogonal experimental design, loss function, and response graphs are used to examine a typical CMOS IG die probe test setup. Particular emphasis was placed on probe needles and contact resistance. Parameters investigated include the probe needle type, test current levels, probe map, probe tip force (or overtravel), and final wafer surface processing. The experiment provided insight into several of the factors affecting probe test resistance, particularly the effects of current and wafer processing on needle resistance. From the results an optimized test setup was established within existing production constraints that minimized probe needle resistance and increased die-per-wafer yield. >
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