Optimizing test architecture of 3D stacked ICs for partial stack/complete stack using hard SoCs

Abstract

Three-dimensional stacked ICs (3D SICs) are currently evolving as an area of great interest in modern semiconductor industry. Several partial stacks tests are required during 3D assembly because the die stacking steps and bonding may introduce defects. In this paper, we have addressed test architecture optimization for 3D stacked ICs implemented with hard dies under the TSV constraints. The main objective of our algorithm is to minimize the test time either for the testing of complete stack or complete stack and several partial stacks. Experimental results are performed for two handcrafted 3D SICs comprising of various system-on-chips from ITC'02 SOC test benchmarks.