Optimizing p-type ultra-shallow junctions for the 65 nm CMOS technology node

Abstract

The limits of using B or BF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> alone in forming ultrashallow junctions have been reached for the 90 nm CMOS generation. In this paper we evaluate the use of Ge and F co-implants to extend conventional implantation and spike anneal to the 65 nm CMOS technology node. In this work we show that the F co-implant can improve the abruptness of the B junction, while the single Ge usually degrades it. The use of Ge co-implanted with F gives the best junction abruptness - less than 5nm/decade. The best trade-off between junction depth (Xj) and sheet resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sheet</sub> ) is achieved by deep Ge pre-amorphization and deep co-implantation of F. A comparison between slow and fast ramp-up is made. Significant improvement for the junction activation, its depth and abruptness is obtained by spike anneal with fast ramp-up for B junctions with Ge and F co-implantation.