Optimizing open-source FPGA CAD tools

Abstract

The development of open-source FPGA CAD tools is challenging. Vendor CAD tools exist but are closed-source and specific to each FPGA family. These tools give limited opportunity for customizing and also have the disadvantage of long compile times. Several open source tools have been built, but the quality of results from these tools is still far behind commercial tools. This research is aimed at bridging some of the gap between commercial and open-source FPGA CAD tools by tuning policies of existing implementation algorithms. We build a set of synthetic benchmarks to identify the mapping between input circuit patterns and policies of a given CAD algorithm and architecture. This work discusses the framework for policy tuning and is aimed at showing that algorithm policies need to adapt to the input circuit. We demonstrate our framework with the packing step of the FPGA CAD flow and show how our approach can be used to improve the quality of results in open-source tools.