Optimizing low-power high-speed full adders with simulated annealing

Abstract

In this paper, a random search algorithm known as simulated annealing (SA) has been employed to optimize the sizing of a number of digital adder circuits. The SA algorithm is implemented in MATLAB; the cost function, a function of power and delay, is accurately computed using HSPICE for a 0.35 /spl mu/m technology. Using a piecewise linear and logarithmic cost function, the delay and power is optimized in an intelligent fashion. The results show a 60% reduction in power and a 65% reduction in delay with respect to previous designs based on analytical calculations.