Optimizing finfet technology for high-speed and low-power design

Abstract

The threshold voltage (Vth) of a FinFET device varies between the on and off mode: Vth is lower when the transistor is on and it is higher when the transistor is off. Such a property is ideal for low-power designs with low supply voltage (Vdd). The low Vth provides high circuit speed even when Vdd is low, while the high standby Vth effectively controls the leakage. In this work, we exploit this property to achieve both high-speed and low-power operations. First, we develop an equivalent sub-circuit model of a FinFET transistor for design explorations. The accuracy of this model is verified with TCAD simulations. Then, we optimize key device parameters to obtain a large range of Vth between dynamic and standby mode: a thicker gate oxide and a thinner silicon body are desirable for this low-power design. Using the optimized FinFET device at 32nm node, we demonstrate that more than 35% reduction in total energy can be achieved without sacrificing the speed. We further benchmark the performance of representative logic and memory units under process variations.