Optimizing Effective Channel Length to Minimize Short Channel Effects in Sub-50 nm Single/Double Gate SOI MOSFETs

Abstract

In the present work a methodology to minimize short channel effects (SCEs) by modulating the effective channel length is proposed to design 25 ㎚ single and double gate-source/drain underlap MOSFETs. The analysis is based on the evaluation of the ratio of effective channel length to natural/ characteristic length. Our results show that for this ratio to be greater than 2, steeper source/drain doping gradients along with wider source/drain rolloff widths will be required for both devices. In order to enhance short channel immunity, the ratio of source/drain roll-off width to lateral straggle should be greater than 2 for a wide range of source/drain doping gradients.