Optimizing Datapaths for Near Threshold Computing

Abstract

Reducing the energy consumption of VLSI circuits is a crucial objective for many modern applications such as the Internet of Things (IoT). The so-called Near-Threshold Computing (NTC) offers about one order of magnitude improvement in the energy efficiency by lowering the supply voltage of a circuit down to the threshold voltage of transistors. As a result of this aggressive voltage scaling, the relative contributions of dynamic and leakage power consumptions to the overall power consumption of a circuit become comparable. However, the aggravated impact of variability sources (20x more) in such a low voltage range hinders the reliability of the NTC circuits, posing an important design challenge. As the assumptions for the power consumption profiles and variation impacts in the NTC are totally different from those of the nominal operating voltage, new optimization techniques are required for power/energy optimization and variability mitigation. In this paper, we discuss cross-layer design techniques for functional units suitable for mitigating variability in the near-threshold voltage regime. As a case study, we evaluate the effectiveness of the proposed techniques on a 64-bit Arithmetic Logic Unit (ALU) by considering circuit, microarchitecture, and architecture level design.