Optimizing Data Placement for Hybrid SRAM+Racetrack Memory SPM in Embedded Systems

Abstract

Nonvolatile memory (NVM) has the potential as the medium for scratchpad memory (SPM) in embedded devices. Racetrack memory (RM), in particular, is a developing memory technology that possesses high density and read latency comparable to SRAM. The RM’s access operations, however, are based on shift operations. Multiple shift operations will lead to long access latency and high energy. In this article, SRAM is borrowed to help the shifts reduction. Thus, a novel hybrid SRAM+RM SPM is presented to make use of SRAM’s random access and RM’s high density. But, there are some challenges to the proposed architecture: 1) the large capacity of SRAM is not available due to its low density and 2) due to the drawbacks of RM mentioned above, data that are randomly accessed are not expected to be stored on RM. Therefore, a data placement scheme and an instruction scheduling strategy are presented for the proposed architecture. First, an access instruction scheduling strategy is introduced to obtain a relatively sequential access sequence to help with the shifts and SRAM size reduction; second, to help with data placement, a metric for representing the data access cost is proposed; third, a data placement strategy based on the metric is proposed; and finally, a solution for decreasing SRAM size is suggested to maximize the capacity of SPM (or minimize the size of SPM). Experiments show that the suggested scheme can significantly improve the performance of the hybrid SPM while also reducing the shifts on RM with minimal SRAM.