Optimizing Behavioral Near On-Chip Memory Computing Systems

Abstract

This work presents an automated design and optimization flow for near on-chip memory computing systems by placing dedicated hardware accelerators directly next to the onchip memory. The salient feature of our proposed flow is that it allows the design of these complex systems completely at the behavioral level, thus, allowing a much richer set of optimizations than traditional Register Transfer Level (RTL) based approaches. Moreover, raising the level of design abstraction allows to quickly evaluate the effect of different optimization on the overall area, performance and power. In addition, it allows to quickly generate system with particular area and performance trade-offs by simply setting different synthesis options' combinations. Experimental results setting different constraints show the effectiveness of our proposed approach.