Abstract

High Efficiency Video Coding (HEVC) is the latest video standard developed by the Joint Video Exploration Team. HEVC is able to offer better compression results than preceding standards but it suffers from a high computational complexity. In particular, one of the most time consuming blocks in HEVC is the fractional-sample interpolation filter, which is used in both the encoding and the decoding processes. Integrating different state-of-the-art techniques, this paper presents an architecture for interpolation filters, able to trade quality for energy and power efficiency by exploiting approximate interpolation filters and by halving the amount of required memory with respect to state-of-the-art implementations.

Highlights

  • Nowadays, the ubiquitous presence of cameras in daily lives requires high video compression efficiency with respect to storage size, bitrate and energy consumption while retaining an acceptable visual quality

  • DCT-based filters are used for the High Efficiency Video Coding (HEVC) fractional pixel interpolation: Pixels at half-sample position (α = 1/2) are originated using the eight-tap filter in contrast to the six-tap one used by H.264/Advanced Video Coding (AVC)

  • Routing Unit (RtU): This redirects the output of the memory bank toward the inputs of the filter

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Summary

Introduction

The ubiquitous presence of cameras in daily lives requires high video compression efficiency with respect to storage size, bitrate and energy consumption while retaining an acceptable visual quality. While the overall functional structure of the two standards is similar, HEVC can provide better results (higher coding efficency, lower bitrates) than H.264/AVC by exploiting a more complex partitioning scheme with many more prediction and transform possibilities [1,2,3]. These algorithmic techniques enable a significant decrease in bitrate at the cost of an increase in computational complexity and external memory bandwidth. HEVC features a two-step motion compensation process, which first works on different search window sizes and exploits an interpolation step for fractional pixel search refinement. Even though this solution consumes the lowest amount of energy per interpolated pixel among state of the art solutions [8,9,10,12], further optimizations can be conceived to reduce the area overhead and to increase the throughput

Contribution
Interpolation Filters
Proposed Architecture
One-Dimensional DCT-IF Architecture
11. Reconfigurable legacy
14. Reconfigurable approximate
Optimized Adder Architectures
Generic Accuracy Configurable Adders
Results and Discussion
Conclusions
Full Text
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