Optimized reversible logic design for Vedic multiplier

Abstract

The performance factors which play a crucial part on any electronic device are power dissipation and operational speed. Any circuit efficiency depends on the performance of the processor that is integrated in it. The components which have a vital role in any processor or computing machine are “multipliers”. Multiplier architecture is designed to improve speed and efficiency in serving complex multiplication operations. One such high speed multiplier is “Vedic multiplier”. The Urdhva Tiryakbhayam (UT) Vedic multiplier is the best solution to increase the operational speed of any device. The newly uprising research area for future low power devices is “reversible logic”. By using the reversible logic, the extreme reduction of power dissipation takes place. UT Vedic multiplier using reversible logic increases the speed of operation and reduces the power dissipation. The required number of constant inputs, gate count and garbage outputs can be reduced by using appropriate reversible logic gates. The Total Reversible Logic Implementation Cost (TRLIC) is to evaluate the proposed design.