Optimized process design flow for fabrication of superjunction VDMOS for enhanced R<inf>DSon</inf>A

Abstract

In this paper, we proposed a simple and optimized process design flow for the fabrication of Silicon Charge Balance (CB) Super Junction (SJ) Vertical Double Diffused MOS (VDMOS). Deep Reactive Ion etching (DRI) is used for forming trench p-pillar with process simulation, which reduces the design complexity and number of steps required for device fabrication. The trench p-pillar that has been formed at 1100° C using DRI causes crystal defects. We remove these defects by annealing at 1150°C which results in reduction of Area Specific ON Resistance across Source/Drain (S/D) (R DSon A). The proposed process device has Breakdown Voltage (BV) 590V, R DSon A 3.1MΩcm2 and maximum operating switching frequency (f T ) 1.027GHz.