Optimized layout on ESD protection diode with low parasitic capacitance

Abstract

The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at GHz RF and high-speed I/O pads in CMOS integrated circuits (ICs) due to the small parasitic loading effect and high ESD robustness. Based on waffle layout style, two modified layout styles have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the figures of merit (FOMs) of ESD protection diodes with new proposed layout styles can be successfully improved.