Optimized Design of an LSSD Scan Cell

Abstract

Type D flip-flop cell and its scannable version called Muxed-D are the most used sequential components in cell-based synchronous designs because it simplifies timing analysis and it is less susceptible to race problems. However, as technology nodes shrink, it becomes more difficult, especially for high-performance designs, to cope with a hard global timing boundary. The use of latches emerges as a possible solution to the contemporary design challenges such as clock skew/jitter, PVT variation, and low-power and high-performance designs. Moreover, latches are also gaining popularity among asynchronous and timing resilient circuits. One of the available scannable cells for latches is called level sensitivity scan-based design (LSSD). The goal of this brief is to present an open design of an optimized single-latch LSSD cell, which has better tradeoffs between propagation delay, power, energy, and silicon area than the original LSSD design, thus reducing the cost for testing latch-based designs.