Optimized buffer protection for network-on-chip based on Error Correction Code

Abstract

Newest technologies of integrated circuits manufacture require a communication architecture such as a Network-on-Chip (NoC). The NoC buffers are susceptible to Multiple Cell Upsets (MCU). Besides, as the technology scales down, the probability of MCU increases. Thus, applying an Error Correction Code (ECC) in NoC buffers may come as a solution for reliability issues, although increasing the design costs and requiring a buffer with higher storage capacity. This work evaluates two models of data arrangement for NoC buffers protected by three types of ECCs, preserving the protection of the storage information, and reducing the area usage and power dissipation compared to other solutions. We evaluated the performance of fault-tolerant NoC buffer schemes by applying the models on three types of ECC and measuring the buffer area, power overhead and error coverage. The experimental results show that the use of the Optimized model keeps the reliability for MCU while reducing area consumption and power dissipation in approximately 25% and 30%, respectively.