Optimization of WiFi Communication System using Low Power Ring Oscillator Delay Cell

Abstract

Modern systems rely on wireless communication for data transmission and system control. Power dissipation and circuit area are crucial factors for such communication systems in portable devices. Ring oscillators are the popular choice for voltage-controlled oscillator (VCO) architecture for Phase locked loop (PLL). This is because ring oscillators exhibit wider tuning range and consume less area on chip. This paper presents a low power ring oscillator designed for wireless application at 5 GHz in the ISM band. A 3-stage starved current voltage-controlled ring oscillator was implemented with 0.13 μm CMOS technology using ELDO Spice simulator from Mentor Graphics. With supply voltage of 1.2V, the power dissipation is 1.08 mW and the phase noise is -78 dBc/Hz at 1 MHz additionally, the proposed ring oscillator with new delay cell layout size occupied 7.1 by 11.7 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .