Abstract
The tunnel field-effect transistor (TFET) is a potential candidate for replacing the reverse diode and providing a secondary path in a whole-chip electrostatic discharge (ESD) protection network. In this paper, the ESD characteristics of a traditional point TFET, a line TFET and a Ge-source TFET are investigated using technology computer-aided design (TCAD) simulations, and an improved TFET-based whole-chip ESD protection scheme is proposed. It is found that the Ge-source TFET has a lower trigger voltage and higher failure current compared to the traditional point and line TFETs. However, the Ge-source TFET-based secondary path in the whole-chip ESD protection network is more vulnerable compared to the primary path due to the low thermal instability. Simulation results show that choosing the proper germanium mole fraction in the source region can balance the discharge ability and thermal failure risk, consequently enhancing the whole-chip ESD robustness.
Highlights
The phenomenon of band-to-band tunneling (BTBT) enables a tunnel field-effect transistor (TFET) to achieve smaller than a 60 mV/dec subthreshold swing (SS) at room temperature [1,2,3]
The integration of TFET and the conventional metal–oxide–semiconductor field-effect transistor (MOSFET) on the same silicon chip is a promising choice for future integrated circuits (ICs) [4]
Silicon-based point TFETs have been investigated in the role of Electrostatic discharge (ESD) protection devices and proposed for use in an ESD protection network [11,12,13,14]
Summary
The phenomenon of band-to-band tunneling (BTBT) enables a tunnel field-effect transistor (TFET) to achieve smaller than a 60 mV/dec subthreshold swing (SS) at room temperature [1,2,3]. The integration of TFET and the conventional metal–oxide–semiconductor field-effect transistor (MOSFET) on the same silicon chip is a promising choice for future integrated circuits (ICs) [4]. Circuit implementations with both TFET and MOSFET proposed in the existing literature have achieved good performance [5,6,7,8]. The results in the aforementioned literature show that the point TFET cannot make a significant contribution to the whole-chip ESD protection due to the low discharge capability. Available solutions are discussed, and simulation results are analyzed in detail
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