Abstract
In this paper, gate misalignment effect have been analyzed in nanoscale double gate (DG) fully depleted (FD) SOI n-MOSFETs, incorporating two important technological issues-graded channel engineering and high-kappa gate dielectrics, using 3-D device simulations. The present work provides a valuable design insight in the performance of nanoscale graded channel DG FD SOI n-MOSFET with high-kappa gate dielectrics incorporating gate misalignment effects and serve as an accurate tool to optimize key device parameters aiding technology development.
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