Abstract
In this paper, an optimization methodology is used to select the locations and characteristics of test, diagnosis and rework operations in electronic systems assembly processes. Real-coded genetic algorithms are used to perform a multi-variable optimization that minimizes the yielded cost of products resulting from an assembly process that includes test/diagnosis/rework operations characterized by costs, yields fault coverage, and rework attempts. A general complex process flow is analyzed using the algorithms proposed in this paper, and a multichip module assembly process flow is used to demonstrate that the methodology can identify optimum test and rework solutions that result in a reduction in yielded cost.
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