Abstract
Scaling transistors into the nano-meter regime has resulted in a dramatic increase in MOS leakage current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Increased transistor leakages not only impact the overall power consumed by a CMOS system, but also reduce the margins available for design due to the strong relationship between process variation and leakage power. Therefore it is essential for circuit and system designers to understand the components of leakage, sensitivity of leakage to different design parameters, and leakage mitigation techniques by designing accurate models of short channel devices and simulating the same using the available standard CAD tools. This paper provides ways to optimize the sub-threshold slope in submicron devices which is an important parameter that defines transistor efficiency in switching applications using standard CAD tools like SILVACO and SPICE
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