Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices.

Qingzhu Zhang,Hong Yang,Renren Xu,Shujuan Mao,Lei Cao,Jie Gu,Jiaxin Yao,Gaobo Xu,Jiajia Tian,Guilei Wang,Zhenhua Wu,Xiaobin He,Jinjuan Xiang,Zhenzhen Kong,Jun Luo,Henry H Radamson,Zhaohao Zhang,Junjie Li,Huaxiang Yin

doi:10.3390/nano11030646

Abstract

In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

Highlights

An effective approach of the GP doping was selected to suppress parasitic sub-fin channels of the 4-layer stacked GAA Si NSs devices based on fin field-effect transistors (FinFETs) fabrication flow
The results show that the n-type and p-type stacked GAA Si NSs devices need different GP doping conditions, and the optimization of parasitic channel for p-type devices is more difficult and complex than that of n-type devices
In order to further study the influence of GP doping on the suppression of parasitic channels and seek out the optimal conditions for p-type stacked GAA Si NSs devices application, 3D technical computer aided design (TCAD) simulations on the stacked GAA Si NSs devices, including process and device simulations, were carried out using Sentaurus TCAD tools

Summary

Introduction

Three-dimensional (3D) fin field-effect transistors (FinFETs) have been widely used for the manufacture of high-volume integrated circuit (IC) products from 22 nm to 5 nm nodes because of their better channel electrostatic controllability and higher driving ability compared to those of conventional planar devices [1,2,3]. As the technology nodes scale down to 5 nm and beyond, many challenges, such as deteriorated electrostatic integrity, irresistible short-channel effects (SCEs), degraded device performance, and large process variability, appear for the FinFET structure [4,5]. Nanomaterials 2021, 11, 646 due to the impact of much stronger control over the gate electrical field, and have been recognized as one of the most promising candidates beyond FinFFT technology [6,7,8,9,10].

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Results

Conclusion