Optimization of SiGe selective epitaxy for source/drain engineering in 22 nm node complementary metal-oxide semiconductor (CMOS)

Abstract

SiGe has been widely used for source/drain (S/D) engineering in pMOSFETs to enhance channel mobility. In this study, selective Si1−xGex growth (0.25 ≤ x ≤ 0.35) with boron concentration of 1–3 × 1020 cm−3 in the process for 22 nm node complementary metal-oxide semiconductor (CMOS) has been investigated and optimized. The growth parameters were carefully tuned to achieve deposition of high quality and highly strained material. The thermal budget was decreased to 800 °C to suppress dopant diffusion, to minimize Si loss in S/D recesses, and to preserve the S/D recess shape. Two layers of Si1−xGex were deposited: a bottom layer with high Ge content (x = 0.35) which filled the recess and a cap layer with low Ge content (x = 0.25) which was elevated in the S/D regions. The elevated SiGe cap layer was intended to be consumed during the Ni-silicidation process in order to avoid strain reduction in the channel region arising from strain relaxation in SiGe S/D. In this study, a kinetic gas model was also applied to predict the pattern dependency of the growth and to determine the epi-profile in different transistor arrays. The input parameters include growth temperature, partial pressures of reactant gases, and chip layout. By using this model, the number of test wafers for epitaxy experiments can be decreased significantly. When the epitaxy process parameters can be readily predicted by the model for epi-profile control in an advanced chip design, fast and cost-effective process development can be achieved.