Optimization of Power-Aware Non-Linearity in Voltage-Controlled Resistive Switching Devices for Non-Volatile Memory Applications

Abstract

This paper reports the optimization of voltage controlled resistive switching devices in terms of device and circuit level parameters in a memristor-based circuit in order to demonstrate profound non-linear characteristics for high performance NVM applications. The pinched hysteresis loop has been correlated to the different stages of formation and rupture of conductive filaments in memristors. A qualitative study of the VTEAM model has also been presented. The memristor circuit has been simulated for varying device and circuit level parameters and options to optimize the circuit to achieve high degree of power-aware non-linearity in the characteristics of the memristor have been demonstrated in this paper. The effect of window functions on the non-linear behavior of memristors has been presented towards the end of the paper.