Optimization of parameters of double-gate sub-20 nanometers SOI CMOS transistors with architecture “without overlapping”

Abstract

One of the possible approaches of an optimum choice of topological parameters of double-gate sub-20 nm CMOS transistors with a silicon-on-insulator structure and architecture that is “without an over-lapping” gate—the extended drain/source areas for minimization of short-channel effects—is discussed. The characteristics of inverters on transistors with a channel length of 16 nm for high-speed applications and applications with a low level of static power are numerically investigated in the power supply voltage range from 0.4 V up to 1 V.