Abstract
Future brain machine interface systems will require recording thousands of neural channels, making it important to minimize the power and area of neural interface integrated circuits. Spike detection is an essential step for neural signal processing. This paper describes the design of a spike detection circuit based on the nonlinear energy operator (NEO) algorithm that is optimized for power and area. Through statistical analysis of NEO coefficients, the number of computations is minimized and the number of registers is shown to be as low as one per channel without degenerating spike detection performance. Based on an analysis of the power-area tradeoff, an optimal 16-channel interleaved architecture is presented and shown to achieve a factor of 4 improvement in power-area product compared to reported NEO implementations.
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