Abstract
This paper describes the optimization method on choice of the metal layers and the Si substrate structure about the 3-Dimantional(3D) vertical solenoid inductor on the CMOS process. The optimization of metal layers that constituted 3D structure inductors enable inductors, in which the two layers (Al, M6) stacked structure with area ratio of 0.3 and the three layers (Al, M6 and M5∼M3) stacked structure with area ratio of 0.17, in comparison with an octagonal planer inductor. In spite of the reduction of area, the peak Q-factor on the inductor is almost equal. As for the constitution under the 3D solenoid inductors, Q-factor of inductor with PGS was lower than that of inductor without PGS, in the case of inductance SR ) of inductor without PGS was higher than that of inductor with PGS. As a result the inductor without PGS is available in a higher frequency domain than the inductor of PGS type.
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