Optimization of Lead Free Plating for Flip Chip Applications

Abstract

Traditional flip chip processes have consolidated to a SnAgCu (SAC) solder system. Each company based upon their own needs and application space has come to their own method to achieve the desired final composition of the interconnect. These have included different solder compositions for both the pre-solder and the C4. The various interconnect solutions can range from no solder on one side such as pure Cu or Ni to an interconnect that has identical solder composition for both the substrate and the C4. Decisions for the optimized solution include the need for reliability, cost and yield. Picking the right solution also enables the elimination of defects such as solder voids, interfacial voids, white bumps, micro-solder bumps and non-wets. The optimized solutions are dependent upon many factors that include the fragility of the silicon dielectric, the size of the die, type of flux used at assembly, the assembly process used, method by which SnAg is plated such as various layering techniques, final processes steps in C4, test probe concepts, DSP methods and many more. In order to pick the appropriate scheme for each product and for each industry, it is imperative to know the interaction of all of these factors. This paper provides concepts and data about how to optimize assembly and lead free plating for a particular process. In the plating process, this includes the importance of various layering steps and analysis of incoming chemicals, especially the acids, and in the assembly process, the knowledge and matching of solder hierarchy, warpage, flux characteristics and preparation / cleaning steps prior to underfill. In particular, we will provide the data and the scheme by which it is possible to produce void free solder processes without bleed and feed on SnAg baths that are over 100 amp-hr per liter and over 1 year old.