Optimization of interconnection layout for multitransistor cell shrinkability

Abstract

The footprint of multi-transistor memory cell is limited by a complex connectivity layout. Depending on the architecture, the interconnect layers might be a hindrance in scaling the cell. This limitation is a result of the need for having multiple contacts to active or gate regions within small cell area as well as by the tight overlay requirements between these contacts and the overlaying metal. Minimum chrome line (i.e., contact space) CD of an attenuated phase shift mask used for printing these contacts as well as the mask and stepper alignment tolerances scale down slower than required by the technology roadmap. Moreover, the novel memory cell applications call for the increased cell complexity. In this work, we discuss how a combination of a new single damascene and self-aligned dual-damascene processes impact the area of a 6-Transistor Double-Wordline SRAM cell. We first identified the optimal cell architecture, followed by developing a unique interconnect scheme. In consequence, the area of the cell was reduced by as much as 25% within the 90 nm technology node. The new interconnect layer has been enabled at the expense of one additional mask.