Optimization of interconnection-induced breakdown voltage in junction isolated IC's using biased polysilicon field plates

Abstract

The detrimental effect of high-voltage interconnection on the blocking capability of a junction isolated (JI) structure in a typical high-voltage integrated circuit (HVIC) process is investigated. A significant increase in breakdown voltage is realized using a novel biased polysilicon field plate technique. Fabricated devices show a large improvement in breakdown over the equivalent junction termination extension (JTE) case for the same wire width. Increases of 30% were observed for a three field plate scheme and 50% for four field plates. Breakdown voltages of up to 700 V were realized for a 50-/spl mu/m wide wire.