Optimization of InP HEMT Using Multilayered Cap and Asymmetric Gate Recess

Abstract

In this research article, we optimize the design metrics of InP (Indium Phosphate) HEMT (High Electron Mobility Transistor) using asymmetric gate recess and multi-layered cap. The device proposed in this paper possesses heavily doped Source/Drain (S/D) region, asymmetric gate recess, multi-layered cap region, InP layer between cap and buffer region. The proposed device incorporates the use of ‘T’ shaped gate and δ (delta) - doping technique. This paper analyzes the RF and DC performances of the device with an In0.52Al0.48As supply layer, In0.65Ga0.35As channel layer built on an InP substrate, with a delta doping of thickness 1 nm, cap layer with varying compositions of InGaAs and a heavily doped S/D region of In0.52Ga0.48As. Complete analysis of the device such as its output characteristics (Drain Current (ID) – Drain Source Voltage (VDS)), transfer characteristics (ID − Gate Source Voltage (VGS)), threshold voltage (from ID - VGS plot), transconductance and transition frequency (fT) are obtained at room temperature (300 K) and the obtained values of these parameters are better as compared to the conventional HEMT because of the abatement of parasitics like S/D resistances. All simulations are performed using Silvaco ATLAS.