Optimization of high-level design edge detect filter for video processing system on FPGA

Abstract

This paper presents the design and the implementation of edge detect filter is optimized for video processing applications on FPGAs. It outlines efficient hardware architecture of spatial filtering (edge detection) for video processing system. This architecture offers a substitute through a graphical user interface that mixes MATLAB, Simulink and Xilinx System Generator that is an extension of Simulink, consisting of a library called “blocks Xilinx”, and explores important aspects interested to hardware implementation. Using Xilinx System Generator in video processing effectively reduces total design time of a system and improves the implementation time. The Hardware-in-the-loop or FPGA in the loop methodology is used in this paper. The objective of this work is to optimize and develop a real-time Hardware Co-Simulation of edge detection system with an input coming from a live video acquired from a digital camera, and outputs are displayed on a video display and verify the video results in real time. The system is implemented on Virtex-5 XUPV5-LX110T FPGA, which provides minimum hardware resources, low power consumption, and high image quality in terms of improved picture signal to noise ratio (PSNR).