Optimization of Graded Buffer Layers for Metamorphic Semiconductor Devices

Abstract

Metamorphic semiconductor devices such as high electron mobility transistors (HEMTs), light-emitting diodes (LEDs), laser diodes, and solar cells are grown on mismatched substrates and typically exhibit a high degree of lattice relaxation. In order to minimize the incorporation of threading defects it is common to use a linearly-graded buffer layer to accommodate the mismatch between the substrate and device layers. However, some work has suggested that buffer layers with non-linear grading could offer superior performance in terms of limiting the surface density of threading defects. In this work, we have compared S-graded buffer layers with different orders and thicknesses. To do so we calculated the expected surface threading dislocation density for each buffer design assuming a GaAs (001) substrate. The threading dislocation densities were calculated using the LMD model, in which the coefficient for second-order annihilation and coalescence reactions between threading dislocations is considered to be equal to the length of misfit dislocations.