Optimization of dual-threshold independent-gate FinFETs for compact low power logic circuits

Abstract

This paper proposes the realization of dual-threshold independent-gate FinFETs by optimizing the FinFET process parameters including the electrode work function, silicon body thickness, and oxide thickness. The optimum values of the FinFET process parameters are derived using BSIM-IMG SPICE model for independent-gate FinFET devices. In optimum dual-threshold independent-gate (IG) FinFETs, a high-threshold IG FinFET is logically equivalent to two short-gate (SG) FinFETs in series, while a low-threshold one is logically equivalent to two SG FinFETs in parallel. The complementary static logic circuits and differential cascode voltage switch logic circuits based on the proposed IG FinFET devices have been verified. The results show that basic gates using the proposed dual-threshold independent-gate FinFETs obtain lower energy delay products than those implementations based on SG FinFETs.