Optimization of Delay Time Stabilization for Single Flux Quantum Cell Library

Abstract

The precise timing analysis of superconducting integrated circuits, particularly cells in a standard cell library, is essential for high-yield superconducting large-scale integration design. In particular, the delay time for individual cells is a crucial timing parameter. Unfortunately, its value is not solely determined by the cell alone but is instead influenced by adjacent cells. In this article, we found that the unstable delay time of a cell is mainly caused by the bias current redistribution in adjacent cells with a certain type of input/output port, which thus requires buffer units for stabilization. Based on this finding, we explored a design method aimed at reducing the influence of adjacent circuits on the timing of a cell of interest, under the premise of the minimization of hardware consumption, and further proposed an optimization scheme to stabilize the delay time.