Optimization of Delay Time between Gate Signals for Si/SiC Hybrid Switch

Abstract

Si and SiC paralleled hybrid switch has been considered to take the advantages of both Si IGBT and SiC MOSFET for high-power applications. The Si/SiC hybrid switch consists of an Si IGBT for better conduction performance and an SiC MOSFET for better switching performance. With the separated gate control signals, the switching moments of the two devices can be controlled independently to ensure Si IGBT under zero-voltage switching (ZVS) conditions to potentially reduce the switching loss of Si IGBT. However, the delay time between two gate signals significantly influences loss reduction of the hybrid switch, which has never been investigated in detail. In this paper, the impact of the delay time on switching characteristics and efficiency improvement of the hybrid switch is investigated. Based on the simulation and experimental results, the optimal delay time is identified to achieve minimum switching loss. By applying the optimal delay time for controlling the gate signals of the hybrid switch, the total switching energy of the hybrid switch is reduced by 35% comparing to the selected IGBT switch.