Abstract
Cu damascene electrodeposition is widely used in the microelectronics industry. A void-free fill electrodeposition process becomes increasingly crucial with the miniaturization of feature dimensions. By optimizing plating process parameters, we demonstrated substantial yield improvement and reliability improvement by reducing voiding defects and improving plated Cu/Cu seed interface during plating. First step pulse is found to be critical for liner/seed/plated Cu interface, and filling current is found to be critical for superfilling rate. In addition, we report here that by using a partial fill partitioning method, we can detect timezero plating defects more effectively than PLY, electrical testing, or cross-section SEM after the completion of Cu plating or after CMP. It plays a critical role in optimizing the process for different technologies and different levels.
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