Optimization of address-based data sorting unit with external memory support

Abstract

Among numerous data processing tasks sorting is considered to be one of the most important. Sorting still poses a big challenge as it actually becomes harder to solve this problem efficiently and fast with the constant demand for processing of larger and larger data sets in a reasonable amount of time. Reconfigurable computing provides an attractive option for implementation of data processing in the context of hardware, as the use of Field Programmable Gate Arrays (FPGAs) allows to eliminate the design constraints of processors and graphics processing units (GPUs) with predefined architectures. In this paper a technique that improves the performance of the address-based data sorting unit with an external DDR3 flag memory is proposed. It is demonstrated that the proposed technique can efficiently reduce the communication penalties associated with the use of external memory.