Abstract
The optimization of critical DC and AC parameters of a double polysilicon bipolar technology for ECL RAM operation is described. In particular, partial factorial arrays and response surface methods are used to optimize simultaneously the current gain and other critical parameters such as cutoff frequency, intrinsic base resistance, emitter-base capacitance, and collector-to-emitter breakdown voltage. The process used is the AMD self-aligned process (ASAP), a self-aligned, trench-isolated, bipolar technology. The use of the optimization method substantially increases the amount of information obtained from a development run, reducing development time and cost. >
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
