Optimization for warpage and residual stress due to reflow process in IGBT modules based on pre-warped substrate

Abstract

Inevitable and severe warpage and stress due to serious mismatch in coefficient of thermal expansion (CTE) between direct bond copper (DBC) plate and copper substrate will be induced into power devices during the reflow process, in which the ambient temperature around the package structure varies from room temperature to die attach solidification temperature and finally to room temperature. The existed warpage and stress or strain can be a hidden danger, and may impact the long-term reliability and durability. This paper investigated warpage and residual stress induced by reflow process in insulated gate bipolar transistor (IGBT) modules by means of the numerical and experimental analysis. The pre-warping of substrate, as an efficient method to reduce final warpage, was quantitatively examined to study effects of the pre-warped copper substrate on final warpage and residual stress in IGBT modules after reflow process. Finite element models considering the viscoplastic behaviors of solder materials and geometric nonlinearity were established to predict the warpage and thermal stress developed in IGBT modules during the reflow process. The aforementioned studies were found to be effective to reduce warpage of entire packaging structure induced by reflow process via finite element method-based simulation validated by experimental measurements.