Abstract
In the high-speed digital printed circuit board, decoupling capacitors play an important role in lowering the power-ground planes impedance leading to the ground bounce noise in I/O ports while the logic is in transition. This paper investigates the optimal placement of decoupling capacitors in suppressing the input and transfer impedances of power-ground planes. The cavity model combines with genetic algorithm (GA) here to find the design specification and the optimal placement of the decoupling capacitors.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
