Optimization for Addition of Partial Product in Vedic Multiplier

Abstract

In digital signal processing applications such as image processing, speech processing, convolution, fast Fourier transform etc. multiplication is one of the important operation to be performed. Application such as encryption, decryption also requires multiplication. Hence performance of multiplier in terms of power, delay and area is important. Design of fast multiplier is required for getting results of different signal processing applications. This paper aims to use vedic multiplication technique for fast, area and power efficient multiplication. Out of 16 sutras of vedic mathematics in this paper UrdhvaTiryakbhyam sutra is used for implementation. For addition of the partial products obtained by UrdhvaTiryakbhyam (vertical and crosswise) multiplication ripple carry adder, carry look ahead adder and proposed method of arrangement of half adders & full adders are used. The different adder schemes are used to improve the delay, area and power of multipliers. The designed multiplier is implemented with VHDL on spartan3 FPGA board using Xilinx ISE 13.1. Power dissipation of implemented multiplier is calculated using XPower analyzer. The proposed design is compared with conventional array multiplier, which resulted in improved speed as well as power of vedic multiplier.