Optimization and implementation of the number theoretic transform butterfly unit for large integer multiplication

Abstract

Fully homomorphic encryption (FHE) is a technique enabling processing to be performed directly on encrypted data in a commercial cloud environment, thereby preserving privacy. Large integer multiplication is the most time-consuming operation during the FHE. Concerning this issue, this paper proposes an operands merging method of the number theoretic transform (NTT) multiplication butterfly unit. By using the operands merging method and a fast modulo method, the operands of the radix-16 units are reduced to 43.8%. The hardware architecture of the NTT radix-16 unit is designed and implemented. The proposed design has been synthesized using 90-nm process technology and Xilinx Kintex UltraScale+ FPGA. The results show that the maximum frequency of the circuit is 600 MHz at the cost of 243k gates and 144 mW and 430 MHz at the cost of 19.6k CLB LUTs, 11.5k CLB registers, and 1.2k CARRY8 respectively. The multiplier implementation results also show that the optimization methods improve the area requirements and performance.