Optimization and hardware implementation of noise reduction algorithm for low‐power audio chip

Abstract

AbstractIn order to improve the voice quality and decrease the power consumption of the audio electronic products, the noise reduction algorithm and its low‐power hardware implementation are studied. Several types of common noise reduction algorithms are analyzed and simulated, and the log‐minimum mean square error algorithm with statistical‐model‐based voice activity detection noise estimator is selected, which can achieve best signal‐to‐noise ratio improvement of 5.56 dB. The ability of the algorithm to track nonstationary noise is analyzed, and the failure of noise reduction caused by an extreme situation is prevented, and the amount of calculation is reduced by multiplex at the algorithm level. In hardware implementation, look‐up tables are used to implement special operations. High‐significant‐bits search is used to simplify the look‐up table to reduce power consumption, and the speed of the search circuit is optimized by parallel design. The exponential integral and exponential operation are combined as one operation with lower precision requirements, leading to lower power consumption. The design presented in this article passed FPGA verification and taped out with a digital hearing aids chip on SMIC 0.13 μm process. The area and the power consumption of the noise reduction module is 0.206 mm2 and 15.3 μW, respectively, which makes the design suitable for low‐power audio chip applications.